This invention relates to semiconductor memory devices and to a technique which will be effective when applied, for example, to CMOS (Complementary MOS) static RAMs (Random Access Memories).
CMOS static RAMs including clocked static decoders are known in the art. A method of improving chip layout efficiency has been proposed by disposing a pre-decoder PDCR shown in FIG. 5 in an X address decoder XDRC of such a CMOS static RAM.
Japanese Pat. Laid-Open No. 74890/1981, for example, describes the address decoder of such a static RAM. This publication is hereby incorporated by reference.
In FIG. 5, the X address decoder XDCR of the CMOS static RAM includes one pre-decoder PDCR and a plurality of NAND gates for decoding represented by a NAND gate circuit NAG 0. Here, the pre-decoder PDCR receives lower 2-bit complementary internal address signals ax0 and ax1 (where an internal address signal such as ax0 having the same phase as an external address signal AX0, and an internal address signal such as ax0 having an opposite phase to the phase of the external address signal AX0 are together expressed as complementary internal address signal ax0), for example, and generates selection signals .phi.x0.about..phi.x3. As represented typically by the NAND gate circuit NAG 0 in FIG. 5, each NAND gate circuit consists of a plurality of N-channel MOSFETs Q.sub.g2 .about.Q.sub.g3 which are connected in series to receive complementary internal address signals ax2.about.axi combined with one another in such a manner as to correspond to the gates of these transistors, and a P-channel MOSFET Q.sub.g1 and an N-channel MOSFET Q.sub.g4 disposed between these MOSFETs Q.sub.g2, Q.sub.g3 and a power source voltage V.sub.cc and ground potential of the circuit, respectively.
As represented by word lines W0.about.W3, each word line of a memory array M-ARY is connected to a word line drive circuit corresponding thereto. These word line drive circuits each consist of a P-channel MOSFET Q.sub.d1 and an N-channel MOSFET Q.sub.d2 connected in a CMOS inverter circuit arrangement. Four word line drive circuits are connected to each decoding NAND gate circuit of the X address decoder XDCR. Each word line drive circuit has the function of a part of the X address decoder XDCR when the corresponding selection signal .phi.x0.about..phi.x3 is supplied from the pre-decoder PDCR described above to the source of the P-channel MOSFET Q.sub.d1 constituting that word line drive circuit.